In electronics and communications devices, it is often important for certain actions to be timed or synchronised. System clocks may be used by electronic components for this purpose. For example, a system clock may be used to control a charge pump. In a charge pump, charge is passed from a voltage supply, via a sequence of capacitors, towards an output. The charge is moved towards the output on each transition of the clock. For a variety of reasons, it may be desirable to reduce the amount of charge being delivered by the charge pump. An integer frequency divider, such as a divide-by-two counter, may be used to reduce the frequency of the system clock by a factor of two. While such components are straightforward to implement, dividing the frequency of the main clock by two may result in a reduction in the transfer of charge in the charge pump to a greater extent than desired.
As an alternative, a non-integer frequency divider may be provided using a phase-locked loops (PLLs). Such an arrangement may allow for a clock to be generated having a frequency that is particular fraction of the system clock frequency. This allows for small reductions in the amount of charge being transferred by the charge pump. However, PLLs can include a relatively large number of components, which take up a large surface area of the device. For a variety of reasons, PLLs may not be available or desired.